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Samsung Hybrid Bonding Technology Expected for Nvidia's Next-Gen AI Accelerator Feynman, Chips to Use Custom HBM

On July 21, Samsung Electronics has started construction of a Die-to-Wafer (D2W) hybrid bonding mass production line at its Pyeongtaek P5 plant, targeting advanced packaging for next-generation HBM and logic semiconductors. The preferred core equipment supplier is Dutch company Besi, with Samsung planning to purchase approximately 50 hybrid bonding machines, each costing about 60 billion won (approximately $4.3 million), which is twice the price of competing products. However, negotiations are progressing slowly due to Samsung's requirement for customized architecture modifications, and Besi, which also supplies TSMC and Micron, is cautious about modifying machines exclusively for Samsung. Samsung is simultaneously considering domestic alternatives: its subsidiary SEMES has completed development of a D2W hybrid bonding machine and sent samples for verification earlier this year; Hanwha Semitech completed development of its second-generation 'SHB2 Nano' in February and sent samples to SK Hynix in April, with its cluster system integrating EFEM, plasma activation, and cleaning modules creating differentiated competitiveness. This technology uses hybrid copper bonding to replace traditional thermocompression bonding, directly bonding copper and dielectric materials, significantly shortening interconnect lengths. The core application scenario is custom HBM—directly stacking HBM DRAM layers vertically on a logic die containing customer computing circuits and IP to form a 3D system-in-package. Citrini analyst Jukan stated that hybrid bonding is expected to be used in Nvidia's next-generation AI accelerator Feynman, which will adopt custom HBM, but the technology's implementation timeline 'has been delayed from HBM4E.' Samsung internally expects mass-scale application around 2029 to 2030, a timeframe that coincides with Nvidia's expected window for Feynman.

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